Keyboard control circuit

ABSTRACT

Controlled avalanche devices such as silicon-controlled rectifiers are used to maximum advantage so that there are dual control paths through the device, one of which may represent a relatively short term function and the other of which may be a relatively long term function, such as, a memory circuit. The inductive EMF of an interrupted inductive circuit is used to extinguish silicon-controlled rectifiers and/or to back bias transistors.

United States Patent Inventor Hugh St. Lawrence Dannatt Rochester, N.Y.

Feb. 3, 1969 Oct. 19, 1971 The Singer Company Appl. No. Filed Patented Assignee KEYBOARD CONTROL CIRCUIT 13 Claims, 1 Drawing Fig.

us. (:1 307/241, 307/252 H, 307/252 K, 317/43 Field of Search 307/241,

[56] References Cited UNITED STATES PATENTS 3,259,829 7/1966 Feth 307/252 X 3,284,740 11/1966 Neapolitakis 307/253 X Primary Examiner-Donald D. Forrer Assistant Examiner-John Zazworsky AttorneysGeorge W. Killian, Patrick J. Schlesinger, Charles R. Lepchinsky and Jay M. Cantor ABSTRACT: Controlled avalanche devices such as siliconcontrolled rectifiers are used to maximum advantage so that there are dual control paths through the device, one of which may represent a relatively short term function and the other of which may be a relatively long term function, such as, a memory circuit. The inductive EMF of an interrupted inductive circuit is used to extinguish silicon-controlled rectifiers and/or to back bias transistors.

CHANNEL l mos 4102 1 R11 IL' I03 PAIENTEnnc 19 |97| AGE/VT Hugh StLawrence Dunncm lm llllll l KEYBOARD CONTROL CIRCUIT BACKGROUND OF THE INVENTION This invention relates to control circuits and, more particularly, to a control circuit employing controlled avalanche devices withamaximum usefulness and efficiency.

The invention herein disclosed is particularly adapted to and disclosed in a business machine environment. In many types of business machines, means are provided fo r' performing a specific function or operation inresponse to the actuation of successive ones of a plurality of key buttons. For example, in the ubiquitous typewriter, a specific character is typed in response to the actuation of a corresponding key; in various calculators, specific computations are initiated in response to key operations; in typesetting machines, selected characters are brought forth in response to key actuations; in tab card order given or executed. That is, it is desirable to be able to determine easily and quickly the nature of the last command given to, or completed by, the machine. In a conventional typewriter, this is quite easily accomplished by a glance at the document. However, in many modern machines,- the last command is not so easily determined. For example, a card punch operator may need to know the last bit of data punched into a card if the operator was distracted and lost her place. Or there are situations wherein an operator is provided with a typewriterlike keyboard but which has no associated printer; the keyboard is used to transmit signals to remote apparatus. In such an application, the operator has a need to be able to determine the last operation.

SUMMARY OF THE INVENTION Accordingly, one of the objects of this invention is to pro- A vide a simple and economical memory which provides an indication of the last command given to, or .executed by, a

controlled avalanche devices.

Another object of the invention is the exploitation of the in- I ductive back electromotive force (EMF) of an inductive ele ment for controlling the conductive state of controlled avalanche devices.

Fufther objects and advantages of the invention will become apparent to those skilled in these and related arts as fjnl following description proceeds, and the features of novelty which 'characterize the invention will be pointed out in partictila rity in the claims annexed to and forming a part of this application.

BRIEF DESCRIPTION OF THE DRAWING v For a more complete understanding of the invention,

. reference may be had to the accompanying drawing which comprises a single sheet and FIGURE and is a schematic circult incorporating the invention.

It should be understood that only the details of the circuit which are necessary for, a full and complete understanding of the invention have been shown. For the most part, conventional symbols have been used to represent conventional circuit parameters. For example, a resistor is illustrated by a sawtooth symbol anda capacitor by two short parallel lines of equal length. The illustrated circuitrequires the application of a DC potential andin order to minimize the number of lines in the drawing, all points connected to the positive terminal of the DC potential are designated Ed and it should be understood that all points so marked are actually connected together and to the positive terminal of the power supply. In a similar manner all points connected to the negative terminal of the DC potential have been designated by a series of parallel lines, each shorter than the previous one until the last is a single dot. In accordance with the practice of the trade, this last symbol and potential is referred to herein as ground." The illustrated circuit employs various solenoids, each of which is represented by a square. Diodes, transistors, and thyristors are illustrated by conventional symbols similar to those illustrated in the GE publication entitled SCR Manual 4the Edition," F. W. Gutzwiller.

The circuit also employs. various mechanical makeand break contacts. In accordance with a symbolism which is gaining favor in the industry, an A," or nonnally open contact, is illustrated by an X in the circuit while a .B, or normally .closed contact, is illustrated bya short line at right angles to Hand bisected by the line representing the wire in which the contact isincorporated. For convenience in circuit analysis, the B4- orpositive terminal symbols are drawn in an upward pointing direction while the negative terminals or ground symbols are drawn in a downward pointing direction. Various other remarks and explanations relating to the circuit and symbolism may be included at appropriate places in the detailed description of the invention. As previously indicated, there are business machine operations which cause the production of perforated tape in ,response to a keyboard operation without the production of.a printed document. In such applications, it is desirable to provide an indication of the last character punched in order that the operatorrnayverify her work. To this end there is provided a plurality of lamps, one for each channel in the tape. The lampsare caused to be illuminated in a code identical to the code last punched into the tape. Accordingly, the lamps provide a memory of the last code punched. By means of a simple conversion chart, the operator can convert the lamp code into the. corresponding alphanumeric character and thereby verify her work.

A keyboard having the mechanical features described herein is disclosed in the Hugh St. Lawrence Dannatt US. Pat. No. 3,327,828 issued June 27, 1967, and entitled Keyboard Mechanism l-Iaving Latching Means." The cited patent is incorporated herein by reference.

The system disclosed in the cited patent employs and discloses a'plura'lity of punch magnets designated PMI to PM8 therein. A greater or lesser number may be used depending upon the punching'code employed. Each punch magnet is connected in substantially the same manner and, therefore, only two areshown herein and designated PMI and PM8. Each punch magnet and associated equipment serves a different channel and, therefore, only two, designated channel I and channel 8', are shown herein.

Connections of the remaining channels are similar to those for channels 1 and 8 with connection to bus leads I01, 102,

example, the lamps associated with punch magnets PM] and PM8:'3I'C designated L1 and L8,-:respectively. In a similar manner, the controlled avalanche devices which in this application constitute silicon-controlled rectifiers are designated SCRI and SCR8; the capacitors are designated C I and C8; the

. switches are designated 51 and S8; and since there are two resistors, they are given second distinguishing digits so that R11 and R12 are associated with punch magnet PMI while R81 and R82 are associated with punch magnet PM8. l1"

Relatively few other components have such a direct associa- .tion with associated components and, therefore, most of the remaining elements are given arbitrary numbers preceded by one or moreletterswhich indicate the nature of the element,

i.e., R for resistor; D for diode; SCR for silicon-controlled rectifier; C for capacitors; and T for transistors. The meaning of any other letters applied to com onents will be explained the first time they are used herein.

Before giving a detailed circuit description, it is believed that a comprehension thereof can be enhanced by providing a few general remarks relating to specific features and characteristics of components employed.

The circuit makes extensive use of controlled avalanche devices such as silicon-controlled rectifiers, for example, elements SCRl to SCR10. It should be understood that devices of this type conduct conventional current from anode to cathode which, as illustrated, is in the direction the triangle representing the device points. However, an SCR does not conduct current even when connected in circuit with a suitable potential source and impedance until the gate element of the SCR has first been coupled to a suitable potential to permit an initial flow of current from the gate to the cathode. Once the anode-to-cathode current has been initiated, the gate potential may be eliminated without any disruption of the anode-to-cathode current. The only ways the anode-tocathode current may be interrupted is by (a) opening the circuit or (b) by providing a sufficient reverse potential between the cathode and anode to actually reverse the current so that there is a small cathode-to-anode current. After action (b) has taken place, the reverse potential may be removed and the forward current will not resume (even though not open circuited) provided the gate is not at the enabling potential.

It should be understood that a wide variety of SCRs are manufactured with a wide range of characteristics. For example, there is a type of SCR in which the gate is connected to the anode rather than the cathode. This last-named type may be used in a circuit incorporating the present invention although, of course, suitable modifications would be required.

A more complete and detailed description of controlled avalanche devices, their characteristics, features, and standard circuits may be found in many sources, one such source being in manufacturers manuals, such as, the cited General Electric SCR Manual.

DESCRIPTION OF THE PREFERRED EMBODIMENT Let it be assumed that power is connected to the apparatus and that it has been in use; that is, keys have been sequentially operated. In this case, various combinations of the punch magnets PMl to PM8 will have been operated and the lamps corresponding to the code for the last character will remain illuminated. As will be shown later, transistors T101 and T102 will be nonconducting and conducting, respectively. With transistor T102 conducting, there is a flow of current from Bl.- to the emitter E and collector C of transistor T102 to bus lead 103 and thence through lamp L1 and SCRl to ground. The current just described will illuminate lamp L1 and SCRl will remain in the conducting state as long as the current described continues to flow. If the current is interrupted by any means, as by a momentary turnoff of transistor T102, the current would not resume if transistor T102 were turned back on. More specifically, SCRl will remain conducting once it has started to conduct so long as the current is not interrupted even though there is no enabling connection to the gate g thereof. As will be seen, only the SCR's 1 to 8 associated with punch magnets that operated will be rendered conducting. Therefore, although transistor T102 applies current to bus lead 103 only those lamps L1 to L8 will be illuminated that are associated with punch magnets which were operated in response to the last input character. Accordingly, the lamps L1 to L8 provide a memory of the last-operated punch magnets.

Transistor T101 is back biased to nonconduction since the base B is more positive than the emitter E. More specifically, there is a current fiow from Brithrough diode D101 and resistor R101 to ground, thereby placing the emitter E of transistor T101 at a potential below B+ by an amount equal to the potential drop across diode D101, this drop being approximately 2 volts. The base B of transistor T101 is at B+ potential, the potential being applied through resistor R102. There is no current flow through resistor R102 as silicon-controlled rectifier SCR9 is not conducting.

In response to the actuation of another key an action, which will be described more fully hereinafter, takes place to back bias and thereby turn off transistor T102 for approximately 1 millisecond. With transistor T102 turned off, all illuminated lamps such as Ll will be extinguished. Transistor T102 will be forward biased after the l-millisecond interval, but no lamps will be illuminated as none of the SCRs remained conducting and none have enabling potential at their respective gates. After the action just described, switch 81, and/or any other of the switches S1 to S8 associated with punch magnets to be operated, will be closed and shortly thereafter switch S101 will close.

In response to the closing of switch S101, B+ potential will be forwarded through the normally closed contacts of switch S102, the now-closed contacts S101 and the bus lead 102. Here the current will divide and pass through one or more of the switches S1 to S8 and hence through resistors R12 and R11 (and/or equivalent resistors associated with switches 82 to S8) to ground. A potential between B+ and ground will thereby be applied to the gate of one or more of the siliconcontrolled rectifiers SCRl to SCR8. In addition, capacitor C1 and/or equivalent in corresponding circuits will be charged. Capacitor C1 furnishes a low-impedance bypass between ground and the gate electrode of the associated SCR thereby providing RFI immunity. In addition, the capacitor integrates the gate signal to ensure adequate gate junction saturation. In a similar manner, current can pass from bus lead 102 through resistors R103 and R104 to ground and to charge capacitor C101 and apply an enabling potential to SCR101.

By means which will be more fully described hereinafter, transistor T101 is turned on and rendered conducting from emitter E to collector C. With transistor T101 conducting, a potential only slightly less than 8+ is placed on bus lead 101 and current is allowed to flow through one or more of the punch magnets PMl to PMS which have had their associated SCRs turned on in the manner described above. More specifically, the current for PMl is from B+ through diode D101, the emitter E to collector C of transistor T101, bus lead 101, punch magnet PMl, diode D11, and SCRl to ground.

The operation of PMl and/or other punch magnets will cause the perforation of a code in tape by means which are well known to those familiar with tape perforators. By means which will be explained more fully hereinafter, transistor T101 will be turned off after sufficient time has elapsed to assure proper and complete operation of any punch magnets PMl to PM8 which were required to be operated.

It should be recognized that transistor T102 was turned on shortly after it had been turned off and that, therefore, the lamps L1 to L8 associated with enabled SCRs will be illuminated; the current for lamp L1 being from 13+ through transistor T102 from emitter E to collector C to bus lead 103 and thence through lamp L1, (and/or any other lamps L2 to L8 associated with enabled silicon-controlled rectifiers) and SCRl to ground. As the cycle of operation continues, the switches S1 and S101 will be opened to remove enabling potential from the gates of SCRI to SCR8. However, it must be observed that removal of the enabling potential will not turn the SCRs off as current is still flowing through selected ones as a result of the current through associated memory lamps such as L1 to L8.

In summary, at the start of a cycle (which follows one or more previous operations) transistor T102 is turned off momentarily to extinguish the memory of the prior code and then the transistor T102 is turned on again to be ready to provide a memory circuit for the next code. Next, transistor T101 is turned on and after a short interval, itis turned off. While transistor T101 is on, selected switches are mechanically closed to enable selected silicon-controlled rectitiers and permit the operation of selected punch magnets. Transistor T101 goes off ending the energization of the selected punch magnets and the mechanical switches are opened to remove the enabling gate potentiaLTransistor T102 remains conducting should be illuminated. If it were not for diode D11,:the current throughv L1 could divide and go up through PMl, back through another punch magnet such as PM8 and thence to ground through SCR8. This and other possible sneak currents are not desirable and, therefore, diodes D11 to D81 are added to prevent such currents.

Clutch magnet CM, diode D9, capacitor C9, resistorsR91 and R92, and silicon-controlled rectifier SCR9 are all connected together in a manner which is similar to the circuit for each punch magnet and itsassociated elements.

Switch S103 is a normally closed contact which is mechanically coupled to the punch cycle so that the switch S103 opens once per cycle of punch operation. With switch S103 closed and no punch cycle in progress, SCR9 is turned off by a means which will be described more fully hereinafter. Bripotential is applied to. the base of transistor T101 through resistor R102 and also to the anode of SCR9 throughresistorRl03 and switch S103. No bias current flows through the base'of transistor T101 as SCR9 is turned off. Obviously, this condition holds transistor T101 off as the base B is positive with j respect to the emitter E.

In response to a signal whose source will be described more fully hereinafter, the gate of silicon-controlled rectifier SCR9 is enabled through resistors R91 and R92 and SCR9 is rendered conducting. With SCR9 conducting, current flows through resistor R102 and R103 and through SCR9 to ground. As a result of the [R drop in resistor R102, the base B of transistor T10] drops to a potential below that of the emitter E and transistor T101 starts to conduct to provide punch magnet current and, as may nowbe seen, current for theclutch magnet CM. Operation of the clutch magnet solenoid CM initiates a punch cycle of operation. Various mechanical opera- I, tions take place and switch contacts S103 open during the cycle. With contacts S103 open, the base bias current for transistoir T101 is interrupted and that transistor turns off.

.With transistor T101 turned off, the current through the clutch magnet CM and the punch magnet is interrupted and ,SCR9 will turn off if it is assumed that the gate current circuit has been opened. lt should be noted that resistor;R104 is of a ,suffieiently high value that the current therethrough'is below ,that of sustaining current for SCR9. The function of R104 is to minimize the characteristic tendency of a silicon-controlled rectifier to turn on without a gate signal in response to the application'of an abrupt potential. The continued presence of potential-at the anode of SCR9 eliminates thefalse turn'on of I sea.

Q When transistor T101 is turned off, the current through the punch magnets rm to ms and the clutch magnet CM is suddenly interrupted. The named elements are inductive and,

therefore,a' back electromotive force maybe produced which might damage the magnets or other circuit components if no provision is made to dissipate the inductive energy. The circuit comprising zenerdiode Z101, diode D102, capacitor C102,

andresistorRlOS provide the requisite diversion and protec- -tion; '1 'he inductive energy is dissipated to ground through the path comprising zener diode Z101 and diode D102. Zener diode'Z101'is selected to zener at approximately 6 volts. By

this. means, the collector terminal of transistor'T101 and bus 101 will be clamped ata potential of approximately 7 volts with respect to ground. While the zener diode 2101 is conducting, capacitor C102 is charged to a potential corresponding to the drop across its parallel-connectedzener diode Z101. As the transient energyis dissipated, the potential of bus lead 101 will drop to approximately 6 volts as capacitor C102 is connected to ground through resistor R105. A negative bias is thus applied to the anodes of silicon-controlled rectifiers SCRl to SCR9, but their diode property prevents reverse current therethrough. By this means, an efi'ective tumoff of SCRl to SCR9 is'achieved even under exceptional conditions of heat, which makes turnoff most difficult. The leakage current of transistor T101 will ultimately discharge capacitor C102 .and terminate the negative bias to silicon-controlled rectifiers corresponds to the cited solenoidactuator of the cited patent.

A restore bail is controlled by release magnet RM. The bail is initially urged byspring force so as to restore mechanical contact encoding means toreset position where contacts such as contacts S101 a'nd'S102, are opened. The mechanical operation is illustrated and described in the cited patent.

For the reasons more fully set forth in the cited patent, the restore magnet is normally held operated when power is applied to the machine and releases once per'cycle of print and/or punchoperation. The release and reoperation of the restore magnet occurs early-in each cycle. The following will explain the circuit which operates the release magnet-RMin response to the original application-of power. Associated with the restore bail is a pair of switches S104 and S105 which are closed when the release magnet RM isnot energized. When places the base of transistor T103 at a negative potential with respect to the emitter, thereby turning ontransistor T103 so that there is current from [H- from the emitter to the collector of transistor T103 and through release magnet coil RM and SCR10 toground. Operation of release magnet RM opens switches S104 and S105. Opening switch S105 turns off transistor T103 but the release magnet RM is held operated in series with resistor R110. Resistor R is of such value that the release magnet will not operate in series with it, but will hold in series with it. Opening switch S104 removes the gate potential from SCR10 but SCR10 remains conducting in accordance with the characteristic thatit remains conducting once it starts toconduct until the current is ihterrupted. The resistor R110 is used to prevent operation of 'RM until transistor T103 is turned on and to reduce the current in RM to a holding value to prevent excess current flow and overheating of magnet RM. Capacitor C10-associated with SCR10 is similar in function to the similar capacitors associated with the silicon-controlled rectifiers SCRl to SCR9.

With silicon-controlled rectifierSCR10 conducting, a path is provided to charge capacitor C103 from 11+ through resistor R11 1, capacitor C103 and to ground through SCR10. Capacitor C103 serves several purposes and, therefore, it will be convenient to keep its state and direction of charge in mind. At

I the present time, capacitor C103 has the lower plate at ground potential and the upper plate at B+ potential.

As previously explained, operation ofa selected key lever results in the generation of an encoded'signal and an initiation of a punch cycle to record the same. Some ancillary features and operations will not be described.

Current is provided from B+ through switches S102 and S101 through resistors R103 and R104 in association with capacitor C101 to provide gate current to silicon-controlled rectifier SCR101 when switch S101 closes at the start of each cycle, With siliconcontrolled rectifier SCR101 turned on, the upper plate of capacitor C103 is suddenly connected to ground potential. Capacitor C103 discharges with energy flowing from its upper plate (which had been at the positive potential) through silicon-controlled rectifier SCR10] to ground and theme in reverse direction through silicon-controlled rectifier SCR10 and back to the lower plate of capacitor C103. With capacitor C103 of sufficient size, the forward current through silicon-controlled rectifier SCR10 may be arrested completely. Accordingly, SCR10 will return to the nonconducting state, release magnet RM will release and restore bail (not shown) will be urged by spring force to restore the operated slides in preparation for the next cycle of operation. Reference should be had to the cited U.S. Pat. No. 3,327,828 for the mechanical details of operation.

Diode D103 and resistor R112 are provided in parallel with the release magnet RM to dissipate part of the inductive energy when the current through RM is terminated. The lastnamed diode and resistor do not dissipate all the inductive energy and the back EMF of the solenoid RM causes the anode of SCR10 to rise momentarily to a potential about 15 volts above that of 8+. Silicon-controlled rectifier SCR10] remains conducting. The potential just described effects a charge on capacitor C103 so that the bottom plate is positive with respect to the upper plate which is at ground potential through silicon-controlled rectifier SCR101.

In response to the release of magnet RM, the restore bail (not shown) will restore under spring force as stated before and switches S104 and S105 will reclose. With switch S104 reclosed, current will flow in resistors R106 and R107 and silicon-controlled rectifier SCR10 will be turned on. Charged capacitor C103 will discharge its stored energy from its positively charged (lower) plate through SCR10 and back through SCR101 to the negatively charged plate. This action turns off SCR101.

The action by which capacitor C103 turns ofi silicon-controlled rectifiers SCR10 and SCR101 is familiar to those skilled in the use of silicon-controlled rectifiers and is known as a commutating process and is described in chapter of the cited General Electric SCR Manual.

With switches S104 and S105 closed, the magnet RM will be operated as previously described, the named switches will be opened and capacitor C103 will be recharged.

As previously pointed out, the transistor T102 is turned off briefly at the start of each cycle in order to erase the memory of the previous cycle. The means by which this is done will now be described.

As shown, the back EMF of solenoid RM raised the potential of the anode of SCR to a value higher than the Bripotential and capacitor C103 was charged. In addition, some current flowed through resistors R113 and R114 to ground and thereby placed the base of transistor T102 at a potential which was positive with respect to the emitter and transistor T102 was turned off, thereby extinguishing all illuminated ones of the lamps L1 to L8 and, therefore, also turning off any of the silicon-controlled rectifiers SCRl to SCR8 which had been conducting. As the transient current of the back EMF decays, the potential at the anode of SCR10 falls to a value less than that of 81+ and transistor T102 returns to conducting condition in preparation to light one or more of the lamps L1 to L8 as a memory of the cycle of operation just starting. The transistor T102 is held turned off for a period of l or 2 milliseconds.

The clutch magnet delay circuit will next be described The clutch magnet circuit employs a silicon bilateral switch designated SBS. The characteristics of this device are described more fully in the cited GE manual. With respect to the present application of the device, it should be noted that the SBS switches into conduction when a voltage exceeding a predetermined value is impressed across it. The SBS is provided with a gate element which is not used in this circuit and, therefore, is not shown in the drawing. It should be recalled that as silicon-controlled rectifier SCR10 was being turned off, its anode rose to a potential about volts above B+. The potential on the anode of SCR10 also charges capacitorC104 in series with resistor R115. As the junction between resistor R1 15 and capacitor C104 reaches a potential of about 8 volts, the silicon bilateral switch SBS changes from a high-impedance to a low-impedance device and permits capacitor C104 to discharge through resistor R116. Capacitor C105 blocks direct current but permits a pulse from said discharge current to render silicon-controlled rectifier SCR9 conducting and thereby initiate a punch cycle as clutch magnet CM is thereby enabled to operate in series with diode D9 and siliconcontrolled rectifier SCR9 when transistor T101 is conducting. The value of resistor R must be so selected and assigned that approximately a 2-millisecond delay is obtained and care must be taken that sufiicient current passes through the silicon bilateral switch SBS so that the circuit configuration does not become a relaxation oscillator.

it should be understood that the purpose of the delay is to guarantee sufficient time to extinguish the prior memory before transistor T101 is rendered conducting. The prior memory is extinguished by the temporary turnoff of transistor T102.

It is well known in the typewriter and allied arts that an experienced operator can sequentially operate a few keys in every familiar combinations at a rate which, if sustained, would be beyond the operating rate of the equipment. It is obviously desirable to include a provision which permits such flurry typing without disturbing the operator's rhythm. ln other words, it is undesirable for the machine to pace the operator. Machine logic requires a certain forbidden period during the cycle of operation wherein data may not be accepted while other data is being processed. Any other action would result in a combination of two codes and obviously an error. Switch S102 controls current from BA- to common contacts S101 and bus lead 102 to individual data channel switches S1 to S8. During the forbidden portion of the cycle, as mentioned above, the switch S102, which is closed when the punch shaft (not shown) is at rest, is caused to open. During the forbidden period, a key may be depressed on the keyboard, a slide may be released, and contacts S101 and one or more of the contacts S1 to S8 may be closed as previously described. Reference to the cited U.S. Pat. No. 3,327,828 will disclose that there is a key-to-key interlock and accordingly only one slide may be released and may rest with the associated contacts closed. Further, key strokes would be inhibited by the said interlock. The selected data will not be processed by the machine until switch S102 recloses at the termination of the forbidden period of the cycle. A subsequent cycle, if already waiting, starts its sequence of operation as if only then initiated. The described system permits the recording of data to proceed with an uninterrupted rhythm up to the maximum speed that the keyboard and the punch mechanism can operate, a speed which may exceed 20 codes per second.

Repeat codes will next be considered. Repeat codes fall into three general classifications, the first of which is the most sim' ple and merely constitutes the reoperation of the last operated key. No special action takes place and it is just as if a new code was presented to the mechanism. Accordingly, no further consideration will be given to this type of repeat action. The two remaining types of repeat codes will next be defined and then considered: 1) Type One: tape feed. In a tape feed operation, a length of tape is processed through a punch in response to the continued depression of a single key. The punching may produce only a feed hole or a delete code, by which is meant a full complement of holes; (2) Type Two: Certain codes such as underline, hyphen, backspace, and carriage return are sometimes desired singly or in multiple sequence. When such codes are desired in multiple sequence, it has become a standard to provide on the associated key a mechanism which permits more than the usual key depression and in response to the greater depression, the multiple operation is generated. The increased depression of the key usually requires the addition of noticeable additional force. This prevents the operator from inadvertently generating repeats.

Repeat codes of type two are initiated by the greater key depression which causes the operation of switch S106. The

first depression of the key records the code in the usual manner and the silicon-controlled rectifiers SCRl to SCR8 remain conducting or not in accordance with the composition of the code. Further depression of the key closes'switches S106 causingcurrent to flow from Brithrough resistor R117 to charge capacitor C106 and through diode D104 to the potentiometerresistors.R92 and R91 and associated capacitor .'.G9,=thus applying current to the gate of silicon-controlled prevent this last possibility, it would be possible to place a resistor in parallel with each of the lamps.

The diode D105 connected .to the base of transistor T102 limits the back bias of said transistor to a safe value.

' Aspointed out above, the back EMF of the punch magnets PMl to PM8 help to turn off their associated silicon-controlled rectifiers. In a similar manner, the. back EMF of clutch rectifier SCR9 which changes to the conducting'state, and allows the operation of clutch magnet CM when. transistor T101 is conducting. With silicon-controlled rectifier SCR9 conducting, current flows from 81+ through resistors R102 and R103, "switch S103 and SCR9 to forward bias transistor T101. .With' transistor T101 conducting, the clutch magnet CM is ener- S8 did not operate at the start of the repeat cycle and that,

' therefore, noaction was started'to release the magnet RM or to turn off transistor T102 to extinguish thememory. During the punch cycle, the contacts S103will open-andthis would normally causetransistor T101 to be back biased and siliconc'ontrolled rectifier SCR9 to be turned 011". However, the currentthrough switch'S106 enables SCR9 to turn on immediate magnets CM contributes to this effect and helps-to turn off SCR9 lf it were not that this'effect is desired, the diode D9 could be eliminated and thelower termin'arof clutch magnet CM; connected directly to ground. The silicon-controlled rectifierSCR9 would not be eliminated,butit wouldno longer carry clu tch magnet current.

By the foregoing, there has been illustrated a practical and 'usefulcircuit employing controlled avalanche devices such as silicon-controlled rectifiers which are used'to maximum advantage in that prior art circuits would have requiredian increased number of components andj'particularly greater number of silicon-controlled rectifiers. I V t It should be'understood that in a system whereinia' lamp display is inappropriate or'not required that the lamp'sfthe controlling transistorTl02, resistors R113 and R lMIand'diodes D11 to D81 and D105 could be eliminated.

ly and as soon as switch S103 reclose's, transistor T101 is forward biased and another cycle of operation will start when clutch magnet CM reoperates. A rapid sequence of identical .codes will thus be recorded at a speed corresponding to the v unclutched shaft speed of the punch. a

Repeat codes of type one will now be considered. If it is desired to provide a tape feed with feed holes only, it is necessary to provide a memory erase function prior to recycling. the

clutch. For this type of tape feed, a key is provided which operates'switches S107 and S108. The operation of S107 is familiar from the description given immediately above as switch S107 obviously initiates an operation which is identical to that for switch S106. However, now the function of capacitor C106 becomes apparent. Capacitor C106 delays the rise of potential to the gate of silicon-controlled rectifier SCR9 and, therefore, SCR9 is not turned on immediately. During the justmentioned delay, switch S108 causes a 8+ potential to be applied to the base of transistor T102, thereby turning it off and extinguishing the memory of the last code. After the delay caused by capacitor C106, the punch performs as described above for repeat codes of type two, the principle difierence being that only feed holes are punched as all memory was erased, thereby extinguishing SCRl and/or any of SCR2 to SCR8 and thereby preventing the reoperation of any punch magnets PMl to PM8 when transistor T101 is turned on.

Repeat codes of type one will now be considered wherein it is desired to provide a tape feed of the delete type, that is, wherein a hole is punched in all channels. In this case, it is necessary to render'all silicon-controlled rectifiers SCRl to SCR8 conducting. The desired objective may be achievedby V providing a key which operates switches S107 and S109 without operating switch S108. As a practical matter, the a switches S108 and S109 may be the same switch and optional "wiring entployed to selectively use it in circuit as shown for switch S108 or S109.As maybe seen,switch S109 applies B+ potentialto bus lead 104 and this signal is applied through a *d iode such asDlZ and D82 for their'respective channels to render the silicon-controlled rectifiers SCRl to SCR8 con- 'ducting. That is, switch S109 provides the same function for all channels that switches S1 to S8 did for their respective channels. The fact that switch S109 is operated results in shifting the memory from that of the last actual code to that of a delete code. The fact that switch S108 is not operated prevents the erasure of any memory. The diodes D12 to D82 prevent feedback or sneak currents through bus 104 when selected ones of the switches S1 to S8 are operated.

It is of interest to point out that if any one of the lamps L1 to L8 burned out, not only would the visual indicator of the last code be lost, but so also would repeat codes be improper. To

' While there has been described for purposes of illusti a'tion a specific form of the invention, it is contemplated that numerous changes may be made without .departing from the spirit of the invention.

While there has been shown and described what is considered at present to be the preferred embodimentof the invention, modifications thereto will readily occur to those skilled in the art. It is not desired, therefore, that the invention be limited to the embodiment shown and described, and it is intended to cover in the appended claims all such modifications as fall within the true spirit and scope of the invention.

What is claimed is:

1 In a control circuit:

a. a controlled avalanche device having cathode and anode electrodes and a control gate;

b. first and second bus leads;

c. a two-terminal potential source;

d. individual circuit means for connecting first and second load impedances between said first and second bus leads, respectively, and one of said electrodes of said device;

e. means connecting the other electrode of said device to one terminal of said potential source;

f. first and second circuit means for selectively connecting the other terminal of said potential source to said first and second bus leads, respectively; and

I g. control means for selectively admitting potential from said potential source to said control gate for rendering said device conductive from said anode electrode to said cathode electrode.

2. The combination as set forth in claim 1 wherein said first and second circuit means may selectively make and break a connection between said-other terminal of said potential source and said first and second bus leads, respectively, in either order and wherein said control means may admit potential from said potential source to said control gate irrespective of the state of connection of said other terminal of said potential source to said first and second bus leads.

3. The combination as set forth in claim 2 wherein said second circuit means maintains said connection of said other terminal of said potential source to said second bus lcad subsequent to breaking said connection-of said other terminal to said first bus lead by said first circuit means and subsequent to the breaking of said connection of said potential source to said control gate by said control means, whereby the current flow is terminated and maintained through said first and second load impedances, respectively.

4. The combinations as set forth in claim 1 wherein said first and second circuit means normally are not and are, respectively, connecting the other terminal of said potential source to said first and second bus leads, respectively, and wherein said control means is normally not admitting potential from said potential source to said control gate.

5. The combination as set forth in claim 4 and including cycle-initiating means coupled to said second circuit means for briefly interrupting the connection between said other ter minal of said potential source and said second bus lead in response to the initiation of a new cycle.

6. The combination as set forth in claim 5 and including delay means coupled to said cycle-initiating means and said first circuit means for causing said first circuit means to connect said other terminal of said source from said first bus a predetermined interval after the initiation of a new cycle of operation. 7

7. The combination as set forth in claim 6 and including cycle control means coupled to said first circuit means for causing said first circuit means to disconnect said other terminal of said source from said first bus a predetermined interval after the initiation of a new cycle of operation.

8. The combination as set forth in claim 1 and including a plurality of said controlled avalanche devices each having individual associated first and second load impedances with said first and second impedance connected between said first and second bus leads, respectively, and one of said electrodes of their associated devices.

9. The combination as set forth in claim 8 wherein an individual control means is associated with each said device.

10. The combination as set forth in claim 9 wherein said first and second circuit means normally are not and are,

respectively, connecting the other terminal of said potential source to said first and second bus leads, respectively, and wherein said individual control means normally are not admitting potential from said potential source to their respective control gate.

11. Circuit control means comprising: a. a direction current potential source; b. first, second, and third bus leads;

c. said third bus lead connected to one terminal of said h. enabling means for selectively applying a suitable potential from said direct current potential source to said gate for rendering said device conducting from said anode electrode to said cathode electrode.

12. The combination as set forth in claim 11 wherein said controlled avalanche device and said first and second two-terminal impedance elements comprise a first assembly and wherein there is a plurality of controlled avalanche devices each connected to associated first and second impedance elements and with each assembly of such elements connected to the first, second, and third bus leads in a manner which is identical to that set forth for said first assembly.

13. The combination as set forth in claim 12 wherein individual enabling means is provided for each controlled avalanche device. 

2. The combination as set forth in claim 1 wherein said first and second circuit means may selectively make and break a connection between said other terminal of said potential source and said first and second bus leads, respectively, in either order and wherein said control means may admit potential from said potential source to said control gate irrespective of the state of connection of said other terminal of said potential source to said first and second bus leads.
 3. The combination as set forth in claim 2 wherein said second circuit means maintains said connection of said other terminal of said potential source to said second bus lead subsequent to breaking said connection of said other terminal to said first bus lead by said first circuit means and subsequent to the breaking of said connection of said potential source to said control gate by said control means, whereby the current flow is terminated and maintained through said first and second load impedances, respectively.
 4. The combinations as set forth in claim 1 wherein said first and second circuit means normally are not and are, respectively, connecting the other terminal of said potential source to said first and second bus leads, respectively, and wherein said control means is normally not admitting potential from said potential source to said control gate.
 5. The combination as set forth in claim 4 and including cycle-initiating means coupled to said second circuit means for briefly interrupting the connection between said other terminal of said potential source and said second bus lead in response to the initiation of a new cycle.
 6. The combination as set forth in claim 5 and including delay means coupled to said cycle-initiating means and said first circuit means for causing said first circuit means to connect said other terminal of said source from said first bus a predetermined interval after the initiation of a new cycle of operation.
 7. The combination as set forth in claim 6 and including cycle control means coupled to said first circuit means for causing said first circuit means to disconnect said other terminal of said source from said first bus a predetermined interval after the initiation of a new cycle of operation.
 8. The combination as set forth in claim 1 and including a plurality of said controlled avalanche devices each having individual associated first and second load impedances with said first and second impedance connected between said first and second bus leads, respectively, and one of said electrodes of their associated devices.
 9. The combination as set forth in claim 8 wherein an individual control means is associated with each said device.
 10. The combination as set forth in claim 9 wherein said first and second circuit means normally are not and are, respectively, connecting the other terminal of said potential source to said first and second bus leads, respectively, and wherein said individual control means normally are not admitting potential from said potential source to their respective control gate.
 11. Circuit control means comprising: a. a direction current potential source; b. first, second, and third bus leads; c. said third bus lead connected to one terminal of said potential source; d. first and second control means for selectively connecting the other terminal of said potential source to said first and second bus leads, respectively; e. a controlled avalanche device having a cathode electrode, an anode electrode, and a gate; f. first and second two-terminal impedance elements having their first terminal connected to said first and second bus leads, respectively, and their second terminals connected to one electrode of said device; g. the other electrode of said device being connected to said third bus; and h. enabling means for selectively applying a suitable potential from said direct current potential source to said gate for rendering said device conducting from said anode electrode to said cathode electrode.
 12. The combination as set forth in claim 11 wherein said controlled avalanche device and said first and second two-terminal impedance elements comprise a first assembly and wherein there is a plurality of controlled avalanche devices each connected to associated first and second impedance elements and with each assembly of such elements connected to the first, second, and third bus leads in a manner which is identical to that set forth for said first assembly.
 13. The combination as set forth in claim 12 wherein individual enabling means is provided for each controlled avalanche device. 